An analog to digital converter (ADC) system typically uses an input driver circuit to sample an analog signal for input to the converter. Depending on the application, there may be a need to manipulate the signal in various ways in order to make use of the capabilities of the ADC. Op amp circuitry is typically used to perform one or more operations such as inverting, attenuating, multiplying, and shifting the input signal to be operated on by the ADC. The ADC cannot convert a moving target, necessitating that the sample of the input signal be held for a period of time. Ideally, a holding capacitor is instantaneously charged to the input voltage, the sampled charge is held for the ADC, and the sample is then converted by the ADC. Departures from the ideal occur in practice due to several problems.
In systems having a capacitive load, op amp sampling circuits have inherent instability problems. Compensation capacitance may be added to offset the phase delay of the capacitive load and keep the system under control, but increasing the compensation capacitor in order to enhance stability has the undesirable side-effect of increasing rise time and reducing bandwidth. As the resolution and speed of ADCs increases, it becomes increasingly difficult to use an op amp to drive the switching input load of high-speed over-sampling ADCs. An approach known in the arts is to attempt to use a feedback network of resistors and capacitors to increase stability. In some instances, the system input driver may be integrated onto the ADC chip to reduce the component count, e.g., the opamp and associated passives, as well as to eliminate a power supply, which is very desirable. In order to arrive at a satisfactory configuration using an opamp to drive a high performance ADC, it is often necessary for the user to make adjustments to the R and C at the input according to performance measurements, making such solutions costly and application-specific.
Spurious free dynamic range (SFDR) is the measure of the difference of the fundamental signal and the largest spur among the samples. The SFDR in general is approximately equal to the worst case signal to noise ratio (SNR). There is a need in the arts for higher bandwidths with both better SNR and SFDR. This in turn means that in order to keep the same over-sampling ratio, the clock frequency as well as the sampling capacitor size must be increased. The SFDR of the sampled signal in these cases is limited by how fast the input amplifier can settle in response to the step at the output caused by the switching load. Since the available time to settle is only one half of a clock cycle, it becomes extremely difficult for the amplifier to settle, to 16-18-bit linearity for example, as the clock frequencies increase, and also as the value of capacitor being switched increases. Traditionally a low pass RC filter is placed in the driver circuit to filter out high frequency thermal noise from the driving opamp and any resistors included in the opamp configuration. This approach becomes less effective as the signal frequency increases, since the −3 db bandwidth of the filter has to be increased to prevent signal attenuation, implying that high frequency thermal noise will necessarily also increase. Moreover, this approach falls short of achieving very good SFDR numbers because the output at the RC filter is a slow moving node and requires a relatively long settling time. This technique works only if the switching capacitor is a very small fraction of the capacitor in the RC filter so that majority of the charge is provided to the capacitor by charge sharing. Additionally, there must be sufficient time for the output to settle for required accuracy. This is generally not the case in high speed over-sampling ADCs. These problems are often encountered in high speed pipelined ADC systems as well as successive approximation register (SAR) ADCs.
Another important practical problem encountered in the arts is that high-speed amplifiers are generally manufactured using BICMOS processes. If the ADC system is implemented using a slow CMOS process to achieve higher swings, then it may not be practical to integrate very fast amplifiers into the system because of the effect of parasitic capacitances on bandwidth and slew rate. One approach known in the arts is to configure a system with a multi-chip module (MCM), having both a BICMOS amplifier and a CMOS ADC together in the same package. However, those familiar with the applicable arts will recognize that this approach to the problem presents additional problems from a manufacturing point of view.
For fully differential circuits, load capacitors switched in the sampling phase are traditionally used, sometimes also with the addition of an RC filter at the driver output. Such a circuit uses a continuous time amplifier with a load capacitor connected during sampling clock phases. Such an amplifier is required to be extremely fast to settle to desired accuracy in one-half clock cycle. It is known to use a pre-charging scheme in SAR converters to relax the requirements on the input driver. The desired effect of this technique is to relax the requirement on the external amplifier by having an internal pre-charge buffer to provide the initial surge current and provide an initial sampling of the input. The pre-charge buffer drives the input during a pre-charge phase, after which the external driver takes over during the sampling phase. One particular disadvantage of this approach is the requirement to use an additional buffer, which means additional power is required. Another problem is that the power consumption for the pre-charge buffer may be excessive.
There is a need in the arts for improved systems and methods for input driver circuits useful for reducing or eliminating one or more of these and possibly other problems, particularly for use in the context of high speed ADC systems.